Introduction to DSP - DSP processors: memory architectures

Although there are many DSP processors, they are mostly designed with the same few basic operations in mind: so they share the same set of basic characteristics. This enables us to draw the processor diagrams in a similar way, to bring out the similarities and allow us to concentrate on the differences:

The diagram shows a generalised DSP processor, with the basic features that are common.

The Analog Devices ADSP21060 shows how similar are the basic architectures:

The ADSP21060 has a Harvard architecture - shown by the two memory buses. This is extended by a cache, making it a Super Harvard ARChitecture (SHARC). Note, however, that the Harvard architecture is not fully brought off chip - there is a special bus switch arrangement which is not shown on the diagram. The 21060 has two serial ports in place of the Lucent DSP32C's one. Its host port implements a PCI bus rather than the older ISA bus. Apart from this, the 21060 introduces four features not found on the Lucent DSP32C:

• There are two sets of address generation registers. DSP processors commonly have to react to interrupts quickly - the two sets of address generation registers allow for swapping between register sets when an interrupt occurs, instead of having to save and restore the complete set of registers.
• There are six link ports, used to connect with up to six other 21060 processors: showing that this processor is intended for use in multiprocessor designs.
• There is a timer - useful to implement DSP multitasking operating system features using time slicing.
• There is a debug port - allowing direct non-intrusive debugging of the processor internals.