To perform the simple arithmetic required, DSP processors need special high speed arithmetic units.
![]() The diagram shows the data path for the Lucent DSP32C processor. The hardware multiply and add work in parallel so that in the space of a single instruction, both an add and a multiply can be completed.
![]() ![]() Registers may be fixed point or floating point format.
![]() The ability to generate new addresses efficiently is a characteristicfe ature of DSP processors. Usually, the next needed address can be generated during the data fetch or store operation, and with no overhead. DSP processors have rich sets of address generation operations:
The table shows some addressing modes for the Lucent DSP32C processor. The assembler syntax is very similar to C language. Whenever an operand is fetched from memory using register indirect addressing, the address register can be incremented to point to the next needed value in the array. This address increment is free - there is no overhead involved in the address calculation - and in the case of the Lucent DSP32C processor up to three such addresses may be generated in each single instruction. Address generation is an important factor in the speed of DSP processors at their specialised operations. The last addressing mode - bit reversed - shows how specialised DSP processors can be. Bit reversed addressing arises when a table of values has to be reordered by reversing the order of the address bits:
This operation is required in the Fast Fourier Transform - and just about nowhere else. So one can see that DSP processors are designed specifically to calculate the Fast Fourier Transform efficiently.
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