The TriMedia CPU core is optimized for multimedia applications. Its design is driven by quantitative testing against benchmarks that define a broad but definite range of media processing domains of applications. The design process targets 'performance in application for lowest chip cost' and leverages many years of experience with consumer electronics and multimedia chip designs.
The TriMedia CPU core uses a Very Long Instruction Word (VLIW) architecture. This has 31 functional units, of which five can be used at any time - leading to very high rates of computation. Some operations implement multiple operations, and some do so also on multiple data items (Single Instruction Multiple Data or SIMD): these 'internally-parallel' operations further increase the parallelsim and speed of the core.
The core CPU is supported by data and instruction caches whose job is to keep the CPU supplied with instructions and data when running at maximum rate.
It is worth noting that the VLIW architecture is very economical for high degrees of parallelism and speed. A superscalar chip (like an Intel "Pentium") has multiple functional units but the scheduling (deciding which operations to perform in parallel) is done at run time, using scheduling silicon on the processor. The scheduling logic costs money and is needed on each chip. The VLIW architecture requires that the instruction scheduling be done at compile time, and is then fixed at run time. This means the scheduling logic can be omitted so the chip is cheaper than a similar superscalar device.